Analog-to-digital converters (ADC) are one of the main components of an electronic receiver. Many receivers are based on a direct-conversion topology, which is employed for receivers that are compatible with multiple standards having different communication frequency bandwidths. The direct-conversion topology utilizes quadrature down-conversion, which includes creating in-phase (I) and quadrature (Q) base-band signals from radio frequency (RF) input signals received by an antenna. FIG. 1 shows a receiver 2 employing the direct-conversion topology. In FIG. 1, an antenna 4 receives an RF signal and sends the RF signal to a filter 6. The output of the filter 6 is amplified by a low noise amplifier (LNA) 8, and the output of the LNA 8 is applied to RF inputs of two mixers 10, 12. The two mixers 10, 12 down convert the RF input signal from the LNA 8 to an I-signal and a Q-signal at base-band frequency using a local oscillator (LO) signal. Typically, the Q-signal is ninety-degrees out of phase with the-I signal. The mixed-down I and Q-signals are filtered using low pass filters 14, 16. After being filtered, the I and Q-signals are input into two ADCs, an I-ADC 18 and a Q-ADC 20, where I-ADC 18 converts the I-signal to a digital signal, and Q-ADC 20 converts the Q-signal to a digital signal. The digital output signals of the I-ADC 18 and Q-ADC 20 are sent to a digital backend 22 for digital processing.
Standards used for wireless communications, such as IEEE 802.11 and Global System for Mobile Communications (GSM), require large frequency bandwidths for each frequency channel so that devices used in wireless environments (e.g., smart phones) can transmit and receive high data rates. When seeking to decrease the size of devices, one common way to reduce the size of the receivers is by reducing the number of stages of the filters in the receiver. However, reducing the number of stages decreases the performance of the filters. In order to offset the decrease in performance of the filters due to the reduction in the number of stages, ADCs having high bandwidth and low noise (i.e., high signal-to-noise (SNR)) performance characteristics are desired.
One type of ADC that yields a high SNR is a sigma-delta ADC. However, in order to meet the high SNR requirement for high-bandwidth signals, the sigma-delta ADC requires at least one multi-bit digital-to-analog converter (DAC), and typically multiple DACs, configured in a feedback loop. For example, a third-order ADC may require three DACs in a feedback loop. In the sigma-delta ADC, after the input signal is sampled by a quantizer, the sampled signal is input to one or more DACs in a feedback loop. Because conventional direct-conversion receiver topologies utilize two ADCs—one for receiving the I signal and one for receiving the Q signal—the total number of quantizers and DACs required is large. The use of multiple DACs in two ADCs thus makes it difficult to decrease the overall size of the analog-to-digital circuitry in a direct-conversion receiver.